As is well known in the prior art, filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects (often referred to as a "Damascene" or a "Dual Damascene" process), requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface. As is also well known in the prior art, the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO.sub.2, SiO.sub.X, or SiO.sub.X N.sub.y); and (c) to be compatible with subsequent electroplating copper thereon.
As is well known, the requirement of providing a low-resistance electrical path is fulfilled by choosing the seed layer to be comprised of an adequately thick, low-resistivity material.
As is further well known, since copper has a rather poor adhesion to oxide surfaces, the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer. As is well known in the prior art, the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds). The barrier layer is often also referred to as an "adhesion layer" or a "liner". In addition to providing good adhesion, the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device. As is well known in the prior art, the barrier layer is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaN.sub.X, Cr, CrN.sub.X, Ti, TiN.sub.X, W, WN.sub.X, and other alloys containing one or more of these materials.
As is still further well known, the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper.
Typically, a seed layer comprises a copper layer that is deposited by a "dry" technique, such as by physical vapor deposition ("PVD"), including but not limited to sputtering or evaporation, or by chemical vapor deposition ("CVD"). However, the seed layer may also be deposited by a "wet" electroless plating process. In such cases, the copper seed layer thickness is typically in a range of about 300 .ANG. to about 2,000 .ANG. on the field (i.e., the top surface of the wafer outside trenches and via openings). In such cases, the barrier layer is typically deposited to a thickness of about 50 .ANG. to about 500 .ANG. (on the field) by either a PVD or a CVD technique.
The PVD techniques include, for example and without limitation, techniques such as evaporation and various sputtering techniques, such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, ion plating, or Ionized Metal Plasma (IMP) sputtering. As is well known in the art, in general, due to their anisotropic and directional ("line of sight") nature, the PVD techniques produce non-conformal deposition. The CVD techniques include, for example and without limitation, thermal CVD, Plasma Enhanced CVD ("PECVD"), Low Pressure CVD ("LPCVD"), High Pressure CVD ("HPCVD"), and Metal Organo CVD ("MOCVD"). For example, one precursor used for CVD Cu is Cupraselect.TM. which is a precursor of Schumacher, Inc. As is well known in the art, in general, due to their isotropic and non-directional nature, the CVD and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings.
Aspect ratio ("AR") is typically defined as a ratio between a vertical dimension, D (depth), of an opening and its smallest lateral dimension, W (width, or diameter): AR=D/W. Usually, in electroplating metals or alloys to fill patterns having high aspect ratio openings (for example, in an insulator or a dielectric), the electroplating rate inside openings is slower than the rate outside openings (i.e., on the field). Further, the higher the AR of the openings, the slower the electroplating rate is inside. This results in poor or incomplete filling (voids) of high AR openings, when compared with results achieved with low AR openings. To overcome this problem in the prior art, commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill. Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating.
The openings may consist of vias, trenches, or patterned photoresist. As is well known, in damascene or dual damascene processes, an insulating or a dielectric layer is pattern-etched to form openings therein. Next, a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings. Next, copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings. Finally, excess plated copper overlying the openings and the top surface (the field) of the insulating layer, as well as the barrier and seed layers on the field, are removed, for example, by a mechanical polishing or by a chemical mechanical polishing ("CMP") technique. The end result is copper filled openings (trenches and vias), including bottom and sidewall surfaces lined by the barrier and seed layers. In today's most advanced copper filling processes for trenches and vias, the openings have ARs as high as 5:1 (D=1.25 .mu.m; W=0.25 .mu.m). Future trenches and vias openings will likely require W=0.13-0.18 .mu.m, or narrower, and AR=6:1-10:1, or larger.
As semiconductor device dimensions continue to shrink, there is an ever increasing demand for narrower interconnect cross-sections and, thus, smaller openings and larger aspect ratios (AR) during the copper electrofill. To ensure void-free copper filling, the seed layer inside the openings must completely cover the bottom and the sidewall surfaces inside the openings without discontinuities, or else there will be voids in the copper electrofill. On the other hand, the seed layer must not be so thick on the sidewalls that it pinches-off the very narrow openings and should not overhang the top corners of the openings so that it pinches-off the very small openings. Similarly, the barrier layer must also be continuous inside the openings. In contrast to these requirements with respect to the openings, the seed layer must be sufficiently thick on the top surface (the field) to provide a low-resistive electrical path that facilitates uniform plating across the surface of the wafer. That is, the seed layer must be sufficiently thick on the field to avoid radial non-uniformity across the wafer caused by a voltage (or IR) drop between a contact at the edge of the wafer to the center of the wafer. Any voltage drop (and resulting non-uniformity therefrom) becomes more severe as the resistance of the seed layer increases due to high resistivity and/or insufficient thickness. To ensure a sufficiently low-resistance seed layer, it is now common to deposit a copper seed layer to a thickness of about 1,000 .ANG. to about 2,000 .ANG. on the top surface (field) by a PVD technique, or to a thickness of about 300 .ANG. to about 1,000 .ANG. by a CVD technique.
However, neither of these techniques satisfies all of the above-identified requirements. The non-conformal PVD techniques, while providing adequate thickness on the field, fail to provide continuous and complete step coverage inside very narrow openings with large AR. They also result in substantial overhangs at the top corners of the openings. The conformal CVD or electroless techniques, on the other hand, while providing continuous and complete step coverage of the seed layer inside very narrow openings, pinch-off the small openings when used at thicknesses required on the field for a low-resistance electrical path. As a result, typical conformal CVD or electroless seed layers are too thin on the field and too thick inside the very narrow openings.
As one can readily appreciate from the above, a need exists in the art for a method for void-free copper filling of very narrow openings having high aspect ratios.